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Japan’s Contributions to Ion Beam Technologies

Isao Yamada

AIP Conf. Proc. 1321, pp. 1-8; doi:http://dx.doi.org/10.1063/1.3548348 (8 pages)

Online Publication Date: 11 January 2011

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In the series of Ion Implantation Technology conferences, several excellent reviews of the history of ion beam technology development have been presented. All of these articles have included descriptions of the evolution of ion implantation equipment and processing. Since 1970, a wide range of other ion beam processing techniques has been developed, not only ion implantation into semiconductor materials for IC fabrication, but also many other techniques for electronic, magnetic and optical devices. In this paper, several of Japan’s important contributions to ion beam technologies and development efforts involving international collaborations in these fields will be discussed.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
85.30.De	Semiconductor-device characterization, design, and modeling
75.50.Kj	Amorphous and quasicrystalline magnetic materials
81.65.Cf	Surface cleaning, etching, patterning

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Evolution of Ion Implantation Technology and its Contribution to Semiconductor Industry

Katsuhiro Tsukamoto, Takashi Kuroi, and Yoji Kawasaki

AIP Conf. Proc. 1321, pp. 9-16; doi:http://dx.doi.org/10.1063/1.3548476 (8 pages)

Online Publication Date: 11 January 2011

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Industrial aspects of the evolution of ion implantation technology will be reviewed, and their impact on the semiconductor industry will be discussed. The main topics will be the technology’s application to the most advanced, ultra scaled CMOS, and to power devices, as well as productivity improvements in implantation technology. Technological insights into future developments in ion‐related technologies for emerging industries will also be presented.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
85.30.De	Semiconductor-device characterization, design, and modeling
61.85.+p	Channeling phenomena (blocking, energy loss, etc.)
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization

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FinFET Doping; Material Science, Metrology, and Process Modeling Studies for Optimized Device Performance

R. Duffy and M. Shayesteh

AIP Conf. Proc. 1321, pp. 17-22; doi:http://dx.doi.org/10.1063/1.3548341 (6 pages)

Online Publication Date: 11 January 2011

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In this review paper the challenges that face doping optimization in 3‐dimensional (3D) thin‐body silicon devices will be discussed, within the context of material science studies, metrology methodologies, process modeling insight, ultimately leading to optimized device performance. The focus will be on ion implantation at the method to introduce the dopants to the target material.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
85.30.Tv	Field effect devices
61.85.+p	Channeling phenomena (blocking, energy loss, etc.)
82.80.Qx	Ion cyclotron resonance mass spectrometry
83.10.Mj	Molecular dynamics, Brownian dynamics

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Novel Approach to Conformal FINFET Extension Doping

G. Zschätzsch, T. Y. Hoffmann, N. Horiguchi, J. Hautala, Y. Shao, and W. Vandervorst

AIP Conf. Proc. 1321, pp. 23-26; doi:http://dx.doi.org/10.1063/1.3548360 (4 pages)

Online Publication Date: 11 January 2011

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This paper presents a novel strategy to achieve conformal FINFET extension doping with low tilt‐angle beam‐line ion implantation. The process relies on the self‐aligned cap layer formation exclusively on top of the FIN to tune doping levels in this particular area by partial dopant trapping. The conformality itself is evaluated for n‐ and p‐type dopants by a novel extraction method applied to FIN resistor test structures. Furthermore, the process was integrated into a full NMOS device flow and compared to a highly tilted and more conformal As implant condition.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
85.30.Tv	Field effect devices
68.37.Lp	Transmission electron microscopy (TEM)
81.15.Cd	Deposition by sputtering

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Plasma Implantation Technology for Upcoming Ultra Shallow and Highly Doped Fully Depleted Silicon On Insulator Transistors

Frederic Gonzatti, Frederic Milési, Vincent Delaye, Julian Duchaine, Frank Torregrosa, Hasnaa Etienne, and Karim Yckache

AIP Conf. Proc. 1321, pp. 27-30; doi:http://dx.doi.org/10.1063/1.3548380 (4 pages)

Online Publication Date: 11 January 2011

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To face the continuous dimensions downscaling for upcoming semiconductor devices, we have investigated a plasma immersion ion implantation way and have compared the results to a conventional one. This new implantation method allows, in particular, high and thin doping concentration to field source and drain requirements for 32 nm node and below. In addition to this key step, a silicon selective epitaxy growth has been performed.

Thus, n‐type and p‐type ion implantations have been carried out on thin blanket SOI substrates in Pulsion® plasma ion implantation tool manufactured by Ion Beam Services, with AsH₃, BF₃ or B₂H₆ precursors. Then a recrystallization annealing followed by silicon selective epitaxial growth has been performed in a reduced pressure chemical vapor deposition tool.

Regarding n‐type implantation we observed a poly‐silicon growth in areas where the top silicon has been amorphous down to the buried oxide and a mono‐silicon growth for areas where the top silicon has not been completely amorphous. Indeed, in this case recrystallization annealing was not sufficient to allow lengthwise solid phase epitaxy growth whereas there were no difficulties for axial one.

Regarding p‐type implantations no epitaxial growths have been observed at all. This lack of growth cannot be explained by a complete silicon amorphization which would have led to a growth of poly‐silicon like for n‐type implantation. According to our first results this growth vacancy could be explained by the very high boron atoms concentration on the substrate surface. The latter being resistant to HF‐last cleaning could thus block silicon nucleation.

However some rinsing processes, more or less aggressive, have been tested to remove this boron silicon alloy layer. Among these different tests, hydrochloric or plasma etching have provided, in some specific cases, promising results allowing an epitaxial silicon growth.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
85.30.Tv	Field effect devices
81.15.Aa	Theory and models of film growth
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization
81.65.Cf	Surface cleaning, etching, patterning

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Advancement of CMOS Doping Technology in an External Development Framework

Amitabh Jain, James J. Chambers, and Judy B. Shaw

AIP Conf. Proc. 1321, pp. 31-36; doi:http://dx.doi.org/10.1063/1.3548397 (6 pages)

Online Publication Date: 11 January 2011

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The consumer appetite for a rich multimedia experience drives technology development for mobile hand‐held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi‐dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI’s core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization
78.40.Fy	Semiconductors
85.40.Bh	Computer-aided design of microcircuits; layout and modeling

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How can we improve sub 40 nm Transistor properties by using Ion implantation

Anbae Lee, Seungwoo Jin, Younghwan Joo, Ilsik Jang, Jaechun Cha, Kichel Jeong, Hyosang Kang, Cjay Cho, Jeonghoon Jang, and Sunny Hwang

AIP Conf. Proc. 1321, pp. 37-40; doi:http://dx.doi.org/10.1063/1.3548426 (4 pages)

Online Publication Date: 11 January 2011

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To extend current process, it is required develop new implantation method. One of promising candidates are carbon implant, cold implant, or cold carbon implantation. To improve transistor properties, we have evaluated those implantation methods in Lightly doped drain (LDD), Source∕Drain(S∕D,P+ BF2, N+ As) and N+ add implant step. Carbon (C+) implantation could improve Short channel effect(SCE), cold implantation decrease Drain induced barrier lowering(DIBL), Sense and amplifer(S∕A) mismatch and contact resistance. Cold carbon implant improved junction Breakdown voltage(BV). Optimization of process conditions and junction profiles is required for optimum device performance.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
85.30.Tv	Field effect devices
81.15.Np	Solid phase epitaxy; growth from solid phases
68.37.Lp	Transmission electron microscopy (TEM)
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)

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Improvement of Poly Profile in Sub 30 nm Device By Damage Engineering and Tilted Implantation Method

Chul‐Young Ham, Noh‐Yeal Kwak, Sang‐Soo Lee, Seung‐Woo Shin, Min‐Sung Ko, Jae‐Mun Kim, Byung‐Seok Lee, Jin‐Woong Kim, Choong‐Young Oh, Yong‐Su Kim, and Benjamin Colombeau

AIP Conf. Proc. 1321, pp. 41-44; doi:http://dx.doi.org/10.1063/1.3548439 (4 pages)

Online Publication Date: 11 January 2011

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Conventionally, P₃₁ out‐gassing of floating gate by succeeding thermal processes happens in NAND FLASH that use floating gate structure, and this P₃₁ out gassing causes degradation of PDR and cell characteristics in sub‐30 nm device. Usually, there is a method to keep PDR of in‐situ doped poly‐Si by increasing the concentration of P₃₁, but this method also causes cell characteristics degradation by trap charge of tunnel oxide.

So, we used another method of ion implantation to control P₃₁ out‐gassing concentration of floating gate by declining effective channel length. If we use methods of low energy and zero tilt implantation, P₃₁ Trap by dopant channeling occurs in tunnel oxide. So, we evaluated methods of low energy and tilted implantation. But in this case, there were poly loss and bending, due to the physical collision damage of implantation.

Therefore, we evaluated the effects of tilt change, direction and temperature control of ion implantation to minimize poly loss of floating gate.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
68.37.Lp	Transmission electron microscopy (TEM)
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)
75.50.Kj	Amorphous and quasicrystalline magnetic materials

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Enabling Solutions for 28 nm CMOS Advanced Junction Formation

C. I. Li, P. Kuo, H. H. Lai, K. Ma, R. Liu, H. H. Wu, M. Chan, C. L. Yang, J. Y. Wu, B. N. Guo, B. Colombeau, T. Thirumal, E. Arevalo, T. Toh, K. H. Shim, et al.

AIP Conf. Proc. 1321, pp. 45-48; doi:http://dx.doi.org/10.1063/1.3548450 (4 pages) | Cited 1 time

Online Publication Date: 11 January 2011

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Controlling short channel effects for further scaled CMOS is required to take full advantage of the introduction of high K∕metal gate or stress induced carrier mobility enhancement. Ultra‐Shallow junction formation is necessary to minimize the short channel effects. In this paper, we will discuss the challenges for 28 nm Ultra‐Shallow Junction formations in terms of figure of merits of Rs∕Xj and junction leakage. We will demonstrate that by adopting and integrating Carborane (CBH, C₂B₁₀H₁₂) molecular implant and Phosphorus along with co‐implantation and PTC II (VSEA Process Temperature Control) technology, sub‐32 nm pLDD and nLDD junction targets can be timely achieved using traditional anneals. Those damage engineering solutions can be readily implemented on state‐of‐the‐art 28 nm device manufacturing.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
72.20.Ee	Mobility edges; hopping transport
68.37.Lp	Transmission electron microscopy (TEM)
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)

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Process Characterization Of Low Temperature Ion Implantation Using Ribbon Beam And Spot Beam On The AIBT iPulsar High Current

Erik J. H. Collart, Ron Teel, Charles Free, Zhimin Wan, Peter Kopalidis, M. A. Razali, Russell Gwilliam, Andy Smith, Edward Tsidilkovski, and Tom Karpowicz

AIP Conf. Proc. 1321, pp. 49-52; doi:http://dx.doi.org/10.1063/1.3548462 (4 pages)

Online Publication Date: 11 January 2011

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The damage and amorphous layer formation properties of a 6 keV 1×10¹⁵ cm⁻² carbon implant were investigated using spot beam and ribbon beam and substrate temperature. The effects of wafer temperature on dopant activation and diffusion were further investigated for boron implants between 300 eV and 2 keV and arsenic implants between 2 keV and 20 keV. The carbon implant amorphization characteristics can be understood using the concept of critical dose for amorphization. B and As activation was found to be 15%–20% improved at the lowest implant temperature but with similar junction depths compared to higher implant temperatures. Higher energy implants showed less or no activation or junction depth improvement at lower implant temperatures.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
75.50.Kj	Amorphous and quasicrystalline magnetic materials
82.80.Qx	Ion cyclotron resonance mass spectrometry
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)
68.37.Lp	Transmission electron microscopy (TEM)

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Implant Damage Studies with Different Implant Temperature by Spot and Ribbon Beam

Hank Chen, Causon Ko‐Chuan Jen, Tony Lin, and Yasuhiko Matsunaga

AIP Conf. Proc. 1321, pp. 53-56; doi:http://dx.doi.org/10.1063/1.3548464 (4 pages)

Online Publication Date: 11 January 2011

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Wafer temperature during implant has a dominate effect on the amorphous layer thickness and post anneal residual defects which can result in difference in device performance and difficulties in tool matching between different implant systems, namely batch type vs. single wafer implanter and spot beam vs. ribbon beam system. Although the implant temperature set point can be well defined and controlled, the instantaneous temperature on wafer during implant is quite complicated interactions among beam shape, dose rate, duty cycle and cooling system to the behavior of defect generation and dynamic annealing. A batch system, iStar, and a single wafer system, iPulsar, which delivers both spot beam and ribbon beam with cold implant capability were used to study the effect of implant temperature to the post anneal residual defects by BF₂ 15 keV 3×10¹⁵ cm⁻² implant after 850 °C∕30s anneal. Measurements from Rs, SIMS, plane view TEM are compared and analyzed. The results by ribbon beam and spot beam are also compared.

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75.50.Kj	Amorphous and quasicrystalline magnetic materials
85.40.Ry	Impurity doping, diffusion and ion implantation technology
68.37.Lp	Transmission electron microscopy (TEM)
61.72.Ff	Direct observation of dislocations and other defects (etch pits, decoration, electron microscopy, x-ray topography, etc.)
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization

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Defectivity Study of PMOS S∕D implants on a Spot Beam High Current Implanter

J. H. Kim, L. M. Rubin, J. Y. Yoon, M. S. Ameen, I. S. Jang, J. C. Cha, Y. H. Joo, A. B. Lee, and S. W. Jin

AIP Conf. Proc. 1321, pp. 57-60; doi:http://dx.doi.org/10.1063/1.3548465 (4 pages)

Online Publication Date: 11 January 2011

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As DRAM devices scale below the 30 nm node, the device performance requirements for the input∕output CMOS circuits are increasing significantly. Specifically, short channel effects (SCE) and their associated leakage currents are becoming increasingly problematic. Various forms of implant damage engineering are being investigated to minimize leakage from SCE. These include changes to the implanter architecture (spot vs. ribbon beam), implantation temperature, and implant species (monomer vs. molecular). We studied the defect morphology both after ion implantation and after annealing for the PMOS S∕D implant on an advanced DRAM device. The implants were combinations of BF₂, (B₁₈H₂₂)₂, C, and C₁₆H₁₀. Implant temperatures ranged from −30 °C to +20 °C. Thermawave, SIMS, Rs and TEM were used to characterize the samples.

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83.50.Ha	Flow in channels
68.37.Lp	Transmission electron microscopy (TEM)
75.50.Kj	Amorphous and quasicrystalline magnetic materials
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization

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Integration of High Dose Boron Implants—Modification of Device Parametrics through Implant Temperature Control

Matthias Schmeide, M. S. Ameen, Serguei Kondratenko, Bernhard Krimbacher, and Ronald N. Reece

AIP Conf. Proc. 1321, pp. 61-64; doi:http://dx.doi.org/10.1063/1.3548466 (4 pages)

Online Publication Date: 11 January 2011

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In the present study, we have extended a previously reported 250 nm logic p‐S∕D implant (7 keV B 4.5×10¹⁵ cm⁻²) process matching exercise [5] to include wafer temperature, and demonstrate that matching can be obtained by increasing the temperature of the wafer during implant. We found that the high dose rate delivered by the single wafer implanter caused the formation of a clear amorphous layer, which upon subsequent annealing altered the diffusion, activation, and clustering properties of the boron. Furthermore, increasing the temperature of the wafer during the implant was sufficient to suppress amorphization, allowing profiles and device parameters to become matched. Figure 5 shows a representative set of curves indicating the cluster phenomena observed for the lower temperature, high flux single wafer implanter, and the influence of wafer temperature on the profiles. The results indicate the strong primary effect of dose rate in determining final electrical properties of devices, and successful implementation of damage engineering using wafer temperature control.

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52.77.Dq	Plasma-based ion implantation and deposition
75.50.Kj	Amorphous and quasicrystalline magnetic materials
68.37.Lp	Transmission electron microscopy (TEM)

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Benefits of Damage Engineering for PMOS Junction Stability

Fareen Khaja, Benjamin Colombeau, Thirumal Thanigaivelan, Deepak Ramappa, and Todd Henry

AIP Conf. Proc. 1321, pp. 65-68; doi:http://dx.doi.org/10.1063/1.3548467 (4 pages) | Cited 1 time

Online Publication Date: 11 January 2011

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As CMOS devices continue to shrink, the formation of ultra shallow junction (USJ) in the source∕drain extension remains to be a key challenge requiring high dopant activation, shallow dopant profile and abrupt junctions. The next generations of sub nano‐CMOS devices impose a new set of challenges such as elimination of residual defects resulting in higher leakage, difficulty to control lateral diffusion, junction stability post anneal and junction formation in new materials. To address these challenges for advanced technological nodes beyond 32 nm, it is imperative to explore novel species and techniques. Molecular species such as Carborane (C₂B₁₀H₁₂), a novel doping species and a promising alternative to monomer Boron is of considerable interest due to the performance boost for 22 nm low power and high performance devices. Also, to reduce residual defects, damage engineering methodologies have generated a lot of attention as it has demonstrated significant benefits in device performance. Varian proprietary techniques to perform implants at cold temperatures (PTC II) have demonstrated lower junction leakage, enhanced activation, reduced dopant diffusion and less dopant deactivation due to the reduction of self‐interstitial atoms present at the end‐of‐range (EOR) with low implant temperatures. In this paper, for the first time, there is a comprehensive study of the effect of implant temperature on defect engineering affecting deactivation∕reactivation, and it is well established in this paper that colder the implant temperature the better it is for damage engineering with reduced EOR defects and better amorphization. The effect has been studied over a wide range of implant temperature. To understand any difference in deactivation between molecular and monomer Boron and to provide direct comparison equivalent Boron implants, co‐implanted with Carbon were also studied. Implants with wide range of temperatures are implemented using PTC II. This paper will also show how damage reduction correlates with optimum junction formation and stability.

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68.55.Ln	Defects and impurities: doping, implantation, distribution, concentration, etc.
61.82.Bg	Metals and alloys
51.20.+d	Viscosity, diffusion, and thermal conductivity
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)
68.37.Lp	Transmission electron microscopy (TEM)

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Doping Technology for the Improvement of Next Generation Device Performance

Kyoichi Suguro

AIP Conf. Proc. 1321, pp. 69-74; doi:http://dx.doi.org/10.1063/1.3548468 (6 pages)

Online Publication Date: 11 January 2011

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This paper reports on the ultra‐rapid thermal annealing of next generation MOSFETs. In ultra‐rapid thermal annealing, the most important issue is to achieve a good balance between electrical activation and impurity diffusion. Another issue of annealing implantation damages is also discussed: Optimized annealing combined with millisecond annealing and conventional halogen lamp annealing is necessary for annealing out defects at end‐of range region. Application possibilities of millisecond annealing for deep junction activation and oxidation are also discussed.

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81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization
85.40.Ry	Impurity doping, diffusion and ion implantation technology
71.55.Ak	Metals, semimetals, and alloys
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)

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A Study of Flash Anneal in combination with the conventional RTA for DRAM application

YoungHo Lee, JinKu Lee, MiRi Lee, SeungJoon Jeon, JaeGeun Oh, Yu. Jun Lee, MinJung Shin, JaeYoung Kim, SeonYong Cha, Kwon Hong, SungKi Park, Tatsufumi Kusuda, Hideo Nishihara, and Kenichi Yokouchi

AIP Conf. Proc. 1321, pp. 75-78; doi:http://dx.doi.org/10.1063/1.3548469 (4 pages)

Online Publication Date: 11 January 2011

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We have investigated the effects of FLA technique on the DRAM peripheral transistor improvements by integrating into the SDRTA (Source∕Drain RTA) and ADD RTA (Add RTA after contact formation). FLA with conventional RTA was not effective because of SCE (Short Channel Effect) control. FLA only was effective to improve SCE and Iop, and especially more effective on technology shrink. By flash anneal (FLA), we tried to achieve better activation, lower series resistance and less dopant loss. For higher activation, the pre‐heat temperature of FLA was varied by 50 °C higher or lower than the desired base temperature. For lower resistance, the sidewall spacer thickness was reduced by 50 Å, 100 Å and 150 Å. For reducing dopant loss during the contact etch process, the deeper S∕D Rp was used by increasing the S∕D implant energy with an increased Rp by 150 Å, 200 Å and 250 Å. Results with FLA base show 13.4% improvement, and at the higher pre‐heat temperature, it can be improved to 16.9%. In conclusion, FLA can be one of the candidates for periperal transistor performance improvement of next generation DRAM device.

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85.30.Tv	Field effect devices
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization
85.40.Ry	Impurity doping, diffusion and ion implantation technology

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Direct Energy Transferred Rapid Thermal Process (RTP) Method and System for Semiconductor Fabrication

Shu Qin

AIP Conf. Proc. 1321, pp. 79-82; doi:http://dx.doi.org/10.1063/1.3548470 (4 pages)

Online Publication Date: 11 January 2011

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A direct energy transferred rapid thermal process (RTP) method is proposed as a new generation RTP to overcome the issues of the conventional RTP and flash‐ or laser‐based anneals. Plasma immersion ion implantation (PIII) is utilized to realize the concept because it can deliver high power density. The ramp‐up rates between 100 °C∕sec and ∼2000 °C∕sec and the effective thermal budgets between seconds and milliseconds can be achieved with other advantages, including no pattern effect, low temperature annealing, high throughput, and flexible process controllability.

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81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization
85.40.Ry	Impurity doping, diffusion and ion implantation technology
85.40.Bh	Computer-aided design of microcircuits; layout and modeling
78.20.Ci	Optical constants (including refractive index, complex dielectric constant, absorption, reflection and transmission coefficients, emissivity)

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Application of Cluster Boron Implantation to pMOSFETs

Y. Kawasaki, M. Ishibashi, M. Kitazawa, Y. Maruyama, S. Endo, T. Yamashita, and T. Kuroi

AIP Conf. Proc. 1321, pp. 83-88; doi:http://dx.doi.org/10.1063/1.3548471 (6 pages)

Online Publication Date: 11 January 2011

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We applied B₁₈H_X⁺ as an alternation of B⁺ or BF₂⁺ to the implantation for source‐drain extension in pMOSFETs corresponding to various technology nodes from 65 nm to 28 nm. We could obtain identical or better characteristics compared to the cases of conventional ions. In addition, we found from blank wafer that larger impact damage to Si atoms in B₁₈H_X⁺ implantation leads to more advantageous R_s‐X_j in activation processing with only MSA.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)
85.30.Tv	Field effect devices
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization

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USJ with ClusterBoron and ClusterCarbon co‐implants

Karuppanan Sekar and Wade Krull

AIP Conf. Proc. 1321, pp. 89-92; doi:http://dx.doi.org/10.1063/1.3548472 (4 pages)

Online Publication Date: 11 January 2011

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ClusterBoron implantation can be used effectively to reduce boron energy while keeping the ClusterBoron energy at a higher level to facilitate better beam transport. With the availability of ClusterBoron species like B₁₈H_x (referred as B₁₈) and B₃₆H_x (referred as B₃₆) along with ClusterCarbon species like C₁₆H_x (referred as C₁₆), it is possible to optimize the dose and energy for both ClusterBoron and ClusterCarbon species to obtain abrupt ultra‐low junction with enhanced boron activation. Cluster implant species (B₁₈, B₃₆ and C₁₆) also provide self‐amorphization leading to amorphous Si layer. Heavier cluster species show larger amorphous layer thickness than the lighter ones for identical implant conditions. In this study we studied the difference between B₁₈ and B₃₆ process with and without a clustercarbon process for 500 eV monomer equivalent boron energies at a dose of 1e15 atoms/cm². The results show that both B₁₈ and B₃₆ process provide better Rs and junction characteristics. The main difference between these two cases is a lower sheet resistance with B₃₆ process when compared to B₁₈ by about 10%. At lower energy (<500 eV), the B₃₆ process show between 20% to 30% lowers Rs than B₁₈. Better self‐amorphization with B₃₆ than B₁₈ is attributed to the lower Rs with B₃₆. With good beam transport at lower energies, B₃₆ offers a production worthy process taking into account the process advantage too.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization
82.80.Nj	Fourier transform mass spectrometry
81.10.Aj	Theory and models of crystal growth; physics and chemistry of crystal growth, crystal morphology, and orientation

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Optimization Of Si:C Stress Retention And Junction Quality With ClusterCarbon Implantation

Karuppanan Sekar, Wade Krull, Jeff Gelpey, and Steve McCoy

AIP Conf. Proc. 1321, pp. 93-96; doi:http://dx.doi.org/10.1063/1.3548474 (4 pages)

Online Publication Date: 11 January 2011

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ClusterCarbon implantation has been shown to be an effective process for making Si:C stressor layer, particularly due to the self‐amorphization feature of cluster implantation. This work is now extended to show that moderate doses of carbon, producing carbon concentrations near the equilibrium solubility, are very effective at producing stress that is stable with respect to thermal treatments necessary for process integration, including spike anneals, which tend to relax such stress. Further, the carbon incorporation challenges the formation of the NMOS junction structures since both carbon and the dopants compete for silicon lattice sites, and excess carbon causes serious deactivation of the dopant species. Here we show that moderate doses of carbon are critical for the simultaneous achievement of retained stress and low resistance junctions. Multiple carbon implant recipes with various n‐type dopant implants and various annealing conditions, including MSA, spike and combination anneals are shown to achieve better carbon substitutionality and re‐crystallization.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
75.50.Kj	Amorphous and quasicrystalline magnetic materials
85.30.Tv	Field effect devices
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)

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Extension of the Si:C Stressor Thickness by Using Multiple ClusterCarbon™ Species

Karuppanan Sekar and Wade Krull

AIP Conf. Proc. 1321, pp. 97-100; doi:http://dx.doi.org/10.1063/1.3548475 (4 pages)

Online Publication Date: 11 January 2011

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ClusterCarbon implantation is now well established as an attractive alternative for producing stress in advanced NMOS devices. ClusterCarbon has the advantage over monomer carbon implant in it’s self‐amorphization feature, eliminating the need for PAI implantation while producing highly substitutional carbon incorporation. To date, the limitation of this approach has been the high energy limit, due to the extraction limit of the available production tools for the preferred carbon species, which has been the C7Hx molecule. It is noted that the C7 species is produced by the breakup of the parent C14H14 molecule in the ion source. It is further noted that the preferred method of producing the Si:C stress layer is a multiple implant sequence with ClusterCarbon implants at various energies and doses designed to produce a carbon profile which is constant in‐depth. The stressor thickness limit using C7 is known to be about 40 nm, which is less than the stressor thickness used in the conventional SiGe process for PMOS. In this work, it is shown that utilizing the C5 molecule which is also available from the breakup of C14H14 enables the stressor layer thickness to be extended to at least 60 nm, which is consistent with the conventional SiGe process. It will be shown that one additional C5 implant, performed after a standard C7 multiple implant sequence, can produce the extension of the stressor thickness while maintaining the flat depth profile. A detailed process characterization will be shown for this new process sequence.

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68.55.Ln	Defects and impurities: doping, implantation, distribution, concentration, etc.
75.50.Kj	Amorphous and quasicrystalline magnetic materials
81.15.Hi	Molecular, atomic, ion, and chemical beam epitaxy
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization

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Larger ClusterBoron® (B₃₆H_x) Implant for USJ Applications

Karuppanan Sekar, Wade Krull, Karim Huet, Celia Boniface, and Julien Venturini

AIP Conf. Proc. 1321, pp. 101-104; doi:http://dx.doi.org/10.1063/1.3548321 (4 pages)

Online Publication Date: 11 January 2011

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The continued scaling of CMOS technology requires that junctions also continue to scale. At the 22 nm node, USJ depth is required to be around 10 nm. While achieving shallower junctions is relatively straightforward by lowering the implant energy, the need to create ever shallower junctions without increasing sheet resistance presents significant challenge. In order to maintain resistance, higher levels of activation are required as junction depth is scaled. In this work, two new technologies are investigated which together form a technology suite which will be shown capable of creating 10 nm p‐type junctions with very high activation. The implant technology uses the dimer of octadecaborane as the implant species and the anneal technology is sub‐microsecond excimer laser anneal.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization
68.37.Lp	Transmission electron microscopy (TEM)
75.50.Kj	Amorphous and quasicrystalline magnetic materials

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Cluster Ion Implantation for Process Application ‐Carbon Cluster co‐Implantation‐

M. Tanjyo, T. Nagayama, H. Onoda, N. Hamamoto, S. Umisedo, Y. Koga, H. Une, N. Maehara, Y. Kawamura, Y. Hashino, Y. Nakashima, M. Hashimoto, N. Tokoro, N. Nagai, K. Sekar, et al.

AIP Conf. Proc. 1321, pp. 105-108; doi:http://dx.doi.org/10.1063/1.3548322 (4 pages)

Online Publication Date: 11 January 2011

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For beyond 32 nm NMOS device fabrication, Cluster Carbon co‐implantation process is experimentally evaluated. It is found that using Cluster Carbon co‐implantation, instead of Ge PAI plus single Carbon co‐implantation, Phosphorus (P) TED was suppressed and the junction depth Xj are reduced by 10 nm for SDE condition and by 17 nm for SD condition when the Cluster Carbon effective dose 2×10¹⁵/cm². The sheet resistivity Rs of 280 Ω∕sq for SDE condition is increased with the increment of the Carbon dose, but the Rs×Xj product 7156 Ω∕sq⋅nm has a minimum value is confirmed. The difference of the Cluster Carbon co‐implantation to the monomer Carbon implantation is evaluated and the Cluster Carbon PAI effect makes higher activation of the P dopnt after annealing.

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85.40.Ry	Impurity doping, diffusion and ion implantation technology
84.37.+q	Measurements in electric variables (including voltage, current, resistance, capacitance, inductance, impedance, and admittance, etc.)
68.43.Jk	Diffusion of adsorbates, kinetics of coarsening and aggregation
68.37.Lp	Transmission electron microscopy (TEM)
61.05.cp	X-ray diffraction

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Formation of Shallow PN Junction by Cluster Boron Implantation and Rapid Annealing Using Infrared Semiconductor Laser

M. Hasumi, K. Ukawa, T. Sameshima, N. Sano, M. Naito, and N. Hamamoto

AIP Conf. Proc. 1321, pp. 109-112; doi:http://dx.doi.org/10.1063/1.3548323 (4 pages)

Online Publication Date: 11 January 2011

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We report shallow PN junctions and analysis of their electrical characteristics. Infrared semiconductor laser annealing using carbon films as optical absorption layer was adapted to the activation of silicon implanted with boron cluster ions. We carried out implantations of boron clusters at 6 keV with an equivalent boron concentration of 1.0×10¹⁵ cm⁻². Laser irradiation at 375 kW/cm² was conducted to activate impurities. Secondary ion mass spectroscopy revealed that boron atoms with a concentration of 6.0×10¹⁴ cm⁻² were incorporated into silicon surface within a 10 nm depth. The free carrier absorption analyses and current‐voltage characteristics of the PN junction diode indicated that the boron atoms were effectively activated by laser annealing.

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85.30.De	Semiconductor-device characterization, design, and modeling
81.40.Ef	Cold working, work hardening; annealing, post-deformation annealing, quenching, tempering recovery, and crystallization
78.20.Ci	Optical constants (including refractive index, complex dielectric constant, absorption, reflection and transmission coefficients, emissivity)
82.80.Qx	Ion cyclotron resonance mass spectrometry
85.30.Kk	Junction diodes

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Advances In The Image Sensor: The Critical Element In The Performance Of Cameras

Tadakuni Narabu

AIP Conf. Proc. 1321, pp. 113-118; doi:http://dx.doi.org/10.1063/1.3548324 (6 pages)

Online Publication Date: 11 January 2011

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Digital imaging technology and digital imaging products are advancing at a rapid pace. The progress of digital cameras has been particularly impressive. Image sensors now have smaller pixel size, a greater number of pixels, higher sensitivity, lower noise and a higher frame rate. Picture resolution is a function of the number of pixels of the image sensor. The more pixels there are, the smaller each pixel, but the sensitivity and the charge‐handling capability of each pixel can be maintained or even be increased by raising the quantum efficiency and the saturation capacity of the pixel per unit area. Sony’s many technologies can be successfully applied to CMOS Image Sensor manufacturing toward sub‐2.0 um pitch pixel and beyond.

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07.05.Pj	Image processing
85.75.Ss	Magnetic field sensors using spin polarized transport
85.60.Gz	Photodetectors (including infrared and CCD detectors)
85.60.Dw	Photodiodes; phototransistors; photoresistors

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